In the design of modern electronic systems, it is increasingly common for large blocks of circuitry to be incorporated into custom integrated circuits known as ASICs, or Application Specific Integrated Circuits. These circuits are typically designed with the assistance of computer-aided engineering (CAE) tools. The actual process of design is such that the designer will use a graphics-based workstation to "draw" schematics of a circuit on the workstation's display screen. This is accomplished by positioning and interconnecting a number of pre-defined circuit elements. Such circuit elements are represented on the display screen by schematic symbols, but also have further, lower level circuit representations associated with them. For example, a logic AND gate may be represented on the designer's display screen as a three terminal device having two inputs and one output. At a lower level, however, there is a representation of that AND gate in the form of a transistor circuit comprising transistors, resistors, etc. It is in this form, that the circuit will actually exist on an integrated circuit when it is completed.
In order for a designer to be certain that his circuit will perform correctly when it is transformed into an ASIC, it is essential that accurate circuit simulation capability be available during the design process. Such simulations must take into account circuit delays, timing dependencies, loading characteristics, and layout induced effects such as parasitic capacitances, etc. These simulations are usually provided in the form of logic and timing models, which allow the designer to closely approximate the performance of his circuit when it is subjected to the stimuli that he specifies. The more accurate the simulation models, the higher the designer's confidence level that the circuit will perform as planned.
A number of tools exist which facilitate the task of ASIC design. Among these are a number of different types of simulators. Each type of simulator operates on a circuit description at a different level of abstraction.
The lowest level simulator is a circuit simulator. One such simulator is SPICE, available under a number of trade names from a number of different vendors. SPICE is a "standard" simulator, which has grown into a de-facto industry standard over a number of years. All SPICE simulators model circuits and their interconnections in the same way, and as such produce very similar results. One commercially available SPICE simulator is HSPICE, produced by Meta-Software Incorporated.
Circuit simulators, such as SPICE and its many variants, model a circuit in very great detail. All circuit elements are modeled in an analog fashion, and transistor models are very complete, taking into account many of the actual physical characteristics of the device. Voltages and currents are modeled as continuously variable entities, rather than the simple one-zero modeling of digital simulators. As a result, circuit-level model results are extremely accurate and highly representative of the performance of actual circuits. Very accurate information about propagation delays and effects of loading, parasitic capacitances, etc., may be derived from circuit-level simulators. Unfortunately, the extreme level of detail used in circuit-level simulation requires a very large number of calculations and restricts their practical use to smaller circuits, or where extremely detailed and accurate information is required.
Switch-level simulators attempt to provide fairly detailed and accurate simulations of digital circuits by modeling all of the transistors in a circuit as switches which may be either closed or open. While this type of model does not deal well with the effects of transistor parameters, for many types of digital logic it provides a reasonably accurate approximation with significantly fewer calculations required than for circuit-level simulators. As a result, fairly detailed and accurate simulation results may be obtained in far less time than is required for circuit level simulation. One commercially available switch-level simulator is TIMEMILL, produced by EPIC Design Technology, Incorporated.
Gate-level simulators are one level of abstraction further away from the circuit than switch-level simulators. Such simulators model a circuit as a group of interconnected logic gates. The logical functions are simple enough to perform, but propagation delays and timing relationships are handled in the form of lumped parameters. Some such simulators will attempt to account for the approximate effects of loading by applying simple equations for propagation delay where the delay is a function of the number of connections. Further, parameters may be passed back from detailed simulations whereby the effects of parasitic capacitances may be approximated, again in the form of a lumped parameter. Gate-level simulators run extremely fast compared to either circuit-level or switch-level simulators, due to the smaller number of calculations required. Provided that the lumped parameters are calculated properly, gate level simulators can provide very reasonable approximations of actual circuit performance. LSI Logic and Mentor Graphics are both commercial sources of gate-level simulators.
One other tool which is commonly made available by vendors of CAE stations and software is timing verification. Timing verification is performed by software which analyzes the timing relationships between logic state changes within a circuit and determines if certain timing criteria such as minimum set-up and hold times have been violated. Timing verifiers do not attempt to model the circuit as it would operate, but rather attempt to analyze the circuit's behavior in the form of relative delays, and cause and effect relationships within a circuit.
Because of the size and complexity of circuits which are commonly put into ASICs, it is essential to the designer that circuit simulations run fast. For this reason, logic simulation of ASICs by the designer is performed almost exclusively through the use of gate-level simulators. In order for gate-level simulation to provide reasonably accurate approximations of actual circuit performance, a fairly extensive process of analysis, simulation and model preparation is required of the tool vendor.
The process of generating logic and timing models for a new circuit element, e.g., gate, flip-flop, adder, etc., is typically a lengthy, labor-intensive process whereby schematics are drawn at both the logic-level and circuit-level. A circuit-level model is generated from the circuit-level (transistor circuit) schematic by means readily available in the present art, usually automatically. The logic circuit and transistor circuits are then analyzed to determine what stimuli should be applied to the circuit level model to arrive at simulation results which will give best indication of the delay characteristics of the circuit. The circuit is laid out and an analysis is performed to determine the effect of adjacent wire runs, etc., on the overall performance of the circuit. The circuit-level simulation is run under several different simulated conditions of power supply voltage and temperature to determine worst and best case delay characteristics, rise and fall times, etc.
The simulation results are examined to determine from the difference in time between critical stimuli and output transitions what values of propagation delay, etc., should be used for the purpose of logic modeling. The logic diagram is annotated with these values in the form of attributes which can be read and acted upon by a logic simulator. Layout induced effects are taken into account, the delay values are altered accordingly, and the logic model is complete.
Timing verification models are usually generated manually based upon data derived from the simulation run and also on knowledge of circuit function and topology. Some logic simulators, such as MDE from LSI Logic Incorporated, combine the functions of logic simulation and timing verification into a multi-mode modeler.
Once a model has been generated, it is common practice to compare the results of circuit-level, switch-level, and gate-level simulations to verify that the results track one another closely. This process is known as model verification. If the models do not track closely enough, the user of a logic simulator will not get accurate representations of the performance of his design, reducing overall confidence that the circuit will perform correctly when it is incorporated into an ASIC.
In the present art, all of the aforementioned simulation, analysis, and parameter extraction operations are performed manually by human operators. Very often, many different people perform different steps in the process, due to the many sets of skills required. Because of the labor-intensive nature of logic/timing model generation and because of the rapid rate of change in the field of digital electronics, it becomes extremely desirable to have a method of automating the process so that accurate logic and timing models may be generated quickly enough to keep up with the needs of the design community, without requiring large, dedicated, highly-trained staffs.